Silicon Chips with 7-Nanometer Density/Memristors/Nanotechnology to Create Powerful Semiconductors with Advantages Over Silicon

The booming AI sector runs on advanced semiconductors (chips), the faster the better. This is fueling a global race to design and manufacture state-of-the-art chips. Demand is growing so quickly that it is reasonable to expect a $1+ trillion global semiconductor market by 2030, roughly double the level of 2023.

This is a highly competitive industry, and China wants a big piece of it. In 2015, China announced plans to invest $161 billion over 10 years in public and private funds aimed at boosting its domestic capabilities in semiconductor research, development and manufacturing. Historically, the nation had been nearly totally dependent on foreign chip technologies but has since made great strides in domestic production. Meanwhile, the U.S. and Taiwan have a compelling lead in global chip manufacturing and engineering. The time, effort, expertise and investment required to launch a new semiconductor plant are immense.

Chips are at the heart of computing devices, including smartphones and laptops, as well as the electronics that run modern factories, research facilities and even automobiles and aircraft. Simply put, chips process information. Silicon, long the traditional material for semiconductors, has limitations. For years, the process of making semiconductors has required a complicated and expensive streamlining of manufacturing techniques for traditional silicon-based chips, with semiconductors becoming faster and faster while chip manufacturing facilities are more and more expensive to build and equip. This process has followed the far-seeing prediction made by former Intel CEO Gordon Moore in 1965 that the number of transistors that could fit on a chip (which translates into processing speed) would double approximately every 18 months. This prediction came to be called “Moore’s Law,” and it held true, more or less, for several decades.

However, continuing the miniaturizing of silicon semiconductors faces immense challenges when vastly more transistors are packed on each chip. This is because traditional circuitry can be limited as it becomes denser, so that it may be unable to conduct electrical currents in an efficient and effective manner. Nanotechnology, using unique molecular structures such carbon nanotubes to create a chip’s transistors and circuitry, promises to solve these problems, creating the ultimate in miniaturization.

While today’s smallest transistors may be only a few molecules across, and billions of transistors may be clustered on each chip, for the future, industry leaders envision transistors and nanoswitches as small as a single molecule or perhaps a single electron. Carbon nanotubes are among the most promising materials of the chip industry’s future.

Denser, Faster Chips: Chip density is the key to faster calculating speed and greater energy efficiency. The nanometer measurement generally refers to the smallest size of a transistor gate (“node number”) contained on a chip. The smaller the measurement, the more transistors that can be incorporated on to a chip. A nanometer is one billionth of a meter. A 4-nano chip can hold 40+ billion transistors in one small, energy-efficient package. (That’s more than 15-times the transistors held on many of 2019’s popular chips.) Apple’s M2 Pro and M2 Max are good examples of these advanced chips, with 40 billion transistors on the M2 Pro 5 nano chip. There is some disagreement as to what actually constitutes the nanometer measurement. One company’s 4-nanometer may be equivalent to another manufacturer’s 5- or even 10-nanometer chip. The industry is evolving the use of nanometers as a measure of overall density of a chip.

Intel’s advanced Meteor Lake CPU architecture (The “Intel 4” platform) was first released at the end of 2023. It is the firm’s first chip to use extreme ultraviolet (EUV) lithography and is considered to be a 7-nm chip. In late 2023, Intel also released its ultrafast Gaudi3 for generative AI systems. Intel planned to release its “Intel 3” fabrication node in 2024 under the code names Granite Rapids and Sierra Forest, both of which will feature exceptionally high core counts and are roughly in the three- to five- nano range.

Chip manufacturer Nvidia has seen soaring demand for its chips. Originally a maker of chips primarily used for gaming, the firm found itself able to capitalize on the extremely fast speeds of its chips to serve the AI processing market. The company launched its latest MI300 in December 2023. The chip features a very significant boost in speed over the previous generation and is well positioned to serve the processing needs of AI large language models (LLMs), including those used for generative AI. The chip is also designed to help server owners combat the immense electricity demands of large AI server installations, as it features advanced energy efficiency technologies.

The Qualcomm Snapdragon X Elite chip was used in high-end Microsoft Surface table as of 2025 and was also designed for artificial intelligence applications. It is capable of running 45 trillion operations per second (TOPS).

Samsung Electronics Co. hoped to begin manufacturing 2-nanometer chips as early as 2025, with a 1.4-nanometer version in 2027. Taiwan Semiconductor Manufacturing Co. (TSMC) expects to produce 2-nanometer chips in 2025.

Intel’s Chip History by Transistor Count

1971: 4004 Processor, 2,300 transistors, 10-micron technology

1982: 286 Processor, 134,000 transistors, 1.5-micron technology

1997: Pentium II Processor, 7.5 million transistors, 0.25-micron technology

2014: Core M Processor, 1.3 billion transistors, 14-nanometer technology

2019: Core X-Series, 3.51 billion transistors (Plunkett Research estimate), 10-nanometer technology

2023: Intel’s 4^th generation Xeon and the Intel Max Series can be used to create server chip sets of over 100 billion transistors each.

Note: One micron = 1,000 nanometers. Several million advanced Intel tri-gate transistors could fit in the period at the end of this sentence.

In 2022, Intel announced a massive $20 billion investment in a new manufacturing site at New Albany, Ohio, east of Columbus. The 1,000-acre location will hold two new plants (fabs), with production startup planned for 2025. Eventually, six additional fabs may be built. Combined, this could comprise the world’s largest semiconductor manufacturing facility. Intel is also investing $36 billion in chip production in Europe, including a new plant in Magdeburg, Germany (the company has an existing chip plant in Ireland). Construction in Germany was expected to begin in 2023 with a completion date in 2027. Additional research and development projects are anticipated in France, Ireland, Italy, Poland and Spain.

The $280 billion Chips and Science Act was signed into U.S. law by President Biden in August 2022. The legislation hopes to spur semiconductor manufacturing in America. It calls for $52.7 billion in direct financial assistance for constructing and expanding manufacturing facilities and adds $24 billion in tax incentives. Micron Technology, Inc. subsequently announced plans to build what will be the largest U.S. semiconductor fabrication facility in upstate New York at a cost of $100 billion. Meanwhile, TSMC and Samsung have each allocated in excess of $100 billion in capital expenditures for new chip plants, over the mid-term.

SPOTLIGHT: Electronics Manufacturers Develop Their Own Semiconductors

For many years, computer, phone and appliance manufacturers have been at the mercy of chipmakers such as Intel Corp. and Qualcomm, Inc. for their vital chip supplies. Some of these manufacturers are choosing to design their own chips and thereby gain control of their own production schedules and product quality. For example, Apple, Inc. began designing its own A-series chips for iPads, iPhones and Apple Watches in 2010. By 2020, it had replaced chips from Intel with its own M-series chips in Mac computers. The in-house chip designs proved to be better suited to Apple’s needs than their Intel counterparts. The chips increased battery life and enabled improved software integration (a boon to the iPhone camera). Apple continues to enhance its chips, with the recent M3 (2023) designs enabling cutting edge video and graphics capabilities.

Other manufacturers are following suit, including Amazon, Google, Tesla and Meta. This trend is possible due to the custom chip manufacturing services offered by third-party fabricators. Such companies accept chip designs from a wide range of clients, and custom make those chips on demand. These companies are referred to as custom “foundries.” Leaders include Taiwan Semiconductor Manufacturing Company (TSMC), GlobalFoundries, ARM and Samsung.

The types of chips that are in the most demand for AI applications include:

= Graphics processing units (GPUs), which are well-suited for training and running AI models.

= Tensor processing units (TPUs), which are designed specifically for AI applications.

= Application-specific integrated circuits (ASICs), which are custom-designed for specific AI applications.

New chip architectures: One of the key trends in AI chip innovation is the development of architectures that are better suited for AI applications. These architectures are designed to improve the performance, efficiency, and power consumption of chips. For example:

= Heterogeneous architectures: These combine different types of processing units, such as CPUs, GPUs and TPUs, into a single chip. This allows the chip to be optimized for different AI workloads.

= ASICs: These are custom-designed chips that are specifically designed for a particular application. This allows the chip to be optimized for improved performance and efficiency.

= Chiplets: In contrast to traditional monolithic chip architecture (which may require the design of entirely new chips in order to create better products or systems), chiplet strategy enables engineers to rapidly design systems that couple together two or more chips in a modular fashion in order to achieve faster or enhanced data processing.

= 3D stacking: This process allows multiple layers of transistors to be stacked on top of each other, resulting in a chip with a higher density of transistors. This can improve performance by allowing it to process more data at once in a parallel fashion.

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