New Semiconductors Provide Higher Speeds and Lower Power Consumption/China Invests in Domestic Chip Manufacturing and Research

The standard process for commercial-use semiconductor manufacturing as of 2016 was 3-D 22-nanometer chips, but this will rapidly evolve to 14-nanometer and smaller chips. Prior to 2007, most manufacturers were building two-dimensional chips using 90-nanometer wafers. Intel’s leap to 45-nanometer technology in 2007 approximately doubled the number of transistors that fit within a given space on a chip. The nanometer measurement refers to the smallest average feature on a chip. The smaller the measurement, the more transistors can be incorporated into a chip of given size. A nanometer is one billionth of a meter. A 22-nanometer chip is small enough that 4,000 of them can be spread across the width of a human hair. Assuming that even smaller transistors are developed about every two years, many analysts expect 5-nanometer chips sometime after 2020.

A significant component in the newer 3-D chip is its ability to greatly limit the leakage of current as it flows across the chip. The raised, 3-D design, called FinFET, has a fin-like structure above the transistor surface, which takes less space on a chip and allows current conduction on three sides, making it much more powerful and features significant energy savings over previous technology. Intel’s 3-D 22-nanometer chips can house about 8.75 million transistors per square millimeter, which makes graphics capabilities inherent in entertainment devices exponentially higher. The first of these chips, code named Ivy Bridge, launched in mid-2012 for use in desktop and laptop processors. In 2013, Intel achieved volume production of 3-D 22-nanometer chips for tablets and smartphones.

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New Semiconductors Provide Higher Speeds and Lower Power Consumption/China Invests in Domestic Chip Manufacturing and Research, Business and Industry Trends Analysis

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